Search results for " arch"

Impact of the erase algorithms on flash memory lifetime

2017

This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance e…

Molecular association of cryptand 221D in NaCl-water solutions. A small-angle neutron scattering study

1993

Molecules of 5-Decyl-4,7,13,16,21-pentaoxa-1,10-diaza-bicyclo-[8.8.5.]tricosan (221D) and its sodium complex, with both a hydrophobic and a hydrophilic portion, are expected to form aggregates in water solutions. This was confirmed by surface tension measurements. The aggregation behaviour was studied by small-angle neutron scattering at two different [NaCl]/[221D] molar ratios, such as to obtain, in one case, aggregates entirely made up of ionic monomers, and in the other, mixed micelles constituted by both ionic and non-ionic units. The variation of the aggregation number and number of aggregates indicated that, in the former case, smaller micelles were formed, as a consequence of repulsi…

L'occupation du site et son contexte environnemental

1998

Enduring Sacred Places: The Astronomical Orientation of the Iberian Cave-Sanctuary of Cueva Santa del Cabriel in Spain

2019

This paper presents the results of an archaeoastronomical study of the Iberian Iron Age cave-sanctuary of Cueva Santa del Cabriel, near the town of Mira in the province of Cuenca, Castilla-La Mancha, central Spain, together with a review of the latest archaeological and ethnographical data about the site. We found that the cave's 12 m-long access corridor is oriented precisely along the summer solstice sunset, so that the north wall of the main gallery is partially illuminated by sunlight at this time. Although the cave was in use from the Late Chalcolithic, it became an important religious centre in the Iberian period. After an apparent hiatus during the Roman and Islamic occupations, its …

Experimental Equipment for Studying the Residual Stresses Developed During High Temperature Reactions by X-Ray Diffraction

1996

This paper describes a device dedicated to studyng, by X-ray diffraction the residual stresses developed on surface samples as a function of temperature and atmosphere conditions. The setup consists of : a.) an horizontal axis goniometer which allows the programmed positionning of the sealed X-ray source and of the linear detector. b.) a high temperature controlled atmosphere chamber Particular attention has been paid to the thermal stability up to 1200°C and the accurate position on the sample.

Preparation, Characterisation and Dielectric Properties of YBa2Cu3O7-δ/ Insulator-Heterostructures

1996

YBa 2 Cu 3 O 7-δ /insulator/Au-heterostructures on SrTiO 3 or LaAlO 3 substrates were prepared to study the properties of the materials SrTiO 3 , BaTiO 3 and Ceo 2 . X-ray diffraction measurements in Bragg-Brentano geometry show c-axis-oriented growth for the superconductor and the insulators SrTiO 3 and CeO 2 . Typical values for the rocking curve width of the different insulating films are between 0.4° and 0.8°. The highest breakdown fields are measured for the insulator SrTiO 3 with +37.5 kV/mm and -8.8 kV/mm. The permittivity for CeO 2 is independent of applied field and only weakly temperature dependent. This is in contrast to the perovskite type insulators, where the permittivity depe…

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

2012

International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…

Evolution of application-specific cache mappings

2020

Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processo…

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

2019

In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…

C-switches: Increasing switch radix with current integration scale

2011

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency, since hop count is also reduced. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we discuss key issues and evaluate an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller single-chip swi…